Advances in integrated circuit design are accompanied by increased challenges for test and verification. For example, increased logic density leads to decreased internal visibility and control, reduced fault coverage and reduced ability to toggle states, more test development and verification problems, increased complexity of design simulation, etc.
Design for test techniques, such as a built-in self test (BIST) and an online test (e.g., a boundary scan) are known. Boundary scan and built-in self test, provide test access to a running fabricated circuit. An example of such a technique is described in the IEEE 1149.1 JTAG standard available from the Institute of Electrical and Electronic Engineers. These methods provide large-scale integrated circuit designers with mechanisms for verifying intended operation.
Generally, a BIST runs the integrated circuit in a test mode that differs from normal circuit operation while checking for faults. An online test checks for faults during normal operation of the integrated circuit. In order to take advantage of the visibility and control provided by BIST interfaces to the functional portions of the integrated circuit under test, online test designers generally require a significant amount of time to learn both the operation of the circuit being tested and the BIST hardware before they can generate productive test cases.
In addition, to the lengthy learning curve, large integrated circuit designs require a significant amount of time to develop a sufficient test that adequately exercises a device under test. Consequently, additional improvements and efficiencies are desired.